An integrated circuit (“IC”) is a semiconductor device that includes many electronic components (e.g., transistors, resistors, diodes, etc.). These components are often interconnected to form multiple circuit components (e.g., gates, cells, memory units, arithmetic units, controllers, decoders, etc.) on the IC. An IC also includes multiple layers of metal and/or polysilicon wiring that interconnect its electronic and circuit components. For instance, many ICs are currently fabricated with five metal layers. In theory, the wiring on the metal layers can be all-angle wiring (i.e., the wiring can be in any arbitrary direction). Such all-angle wiring is commonly referred to as Euclidean wiring. In practice, however, each metal layer typically has one global preferred wiring direction, and the preferred direction alternates between successive metal layers.
Many ICs use the Manhattan wiring model that specifies alternating layers of horizontal and vertical preferred direction wiring. In this wiring model, the majority of the wires can only make 90 degree. turns. Occasional diagonal jogs are sometimes allowed on the preferred horizontal and vertical layers. Standard routing algorithms heavily penalize these diagonal jogs (i.e. assess proportionally high routing-costs), however, because they violate the design rules of the Manhattan wiring model. Some have recently proposed ICs that use a diagonal wiring model to provide design rules that do not penalize diagonal interconnect lines (wiring). Interconnect lines are considered “diagonal” if they form an angle other than zero or ninety degrees with respect to the layout boundary of the IC. Typically however, diagonal wiring consists of wires deposed at .+−.45 degrees.
Typical Manhattan and diagonal wiring models specify one preferred direction for each wiring layer. Design difficulties arise when routing along a layer's preferred direction because of obstacles on these wiring layers. For example, design layouts often contain circuit components, pre-designed circuit blocks, and other obstacles to routing on a layer. Such obstacles may cause regions on a layer to become essentially unusable for routing along the layer's single preferred direction.
An example that shows obstacles that cause regions on a design layout to become unusable for routing is illustrated in FIG. 1. This figure shows two wiring layers that each have two routing obstacles 115 and 120. One of the layers has a horizontal preferred direction; the other layer has a diagonal preferred direction. The obstacles 115 and 120 cause two regions 105 and 110 to become unusable for routing on both of these layers. Therefore, both the Manhattan and diagonal wiring models typically waste routing resources on the layers of a design layout.
U.S. Ser. No. 11/005,316, which is the parent to this application, describes a wiring model that allows Manhattan and diagonal wiring and recaptures the routing resources loss because of obstacles on a wiring layer. More generally, there is a need for a route planning method that maximizes the routing resources on each particular layer.